The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a semiconductor fin using double trench epitaxy.
In each new generation of semiconductor technology, transistor current tends to decrease due to gate width reduction, mobility degradation of minority carriers, and reduction of supply voltage. Reduced transistor current may result in deterioration of circuit stability and may reduce the speed of circuit operation, both of which may cause degradation in performance.
In some field effect transistor (FET) devices, one layer may be formed on another layer having a substantially different crystal lattice constant, which may result in significant strain on the subsequently formed layer. For instance, conventional methods of heterointegration of III-V compounds on materials such as silicon may result in strain within a III-V compound layer. Significant strain on a layer may result in crystal lattice defects that may spread throughout a volume of the layer during formation. The performance of devices fabricated using dissimilar semiconductor materials can be materially affected by defects that cause abrupt changes in electrical and/or optical properties. Adverse effects due to misfit defects and threading dislocations should be minimized or avoided in the fabrication of electronic devices incorporating such semiconductor materials.
In addition, conventional methods for forming a fin in a fin field effect transistor (FinFET) device may result in fin patterning deformations, such as tapering and roughness. Patterning deformations may reduce performance in a FinFET device. Thus, patterning deformations in a fin should be minimized or avoided in the fabrication of FinFET devices.